We are buffer and pipeout to transfer data to PC.
We have two questions using it.
a) Do you have to pass the data in size which is multiple of 16bytes in size?
b) Debugging from FPGA, the data sent seems fine, but received data in PC is shifted as example below.
4 bytes are added in the front. I am using ReadFromPipeOut function for it.
for example) data sent: 0x0A 0x0B 0x0C 0x0D…
data received: 0x00 0x00 0x00 0x00 0x0A 0x0B 0x0C 0x0D…
What should be the problem for this kind of situation.
From FPGA, I am sending a one cycle of clock to PC.
To check the trigger, PC repeats “UpdatesTriggerOuts” and “IsTriggered” to findout the rising edge of trigger. But looking at “IsTriggered”, it never returns true.
I don’t think I have to check the accurate timing between a cycle from fpga and updatestrigger.
Also are there any detail document about pipe out and trigger out please give us some information about it.