Hi Support Team
Does ReadFromPipeOut call support any Read latency ? Per the signal /waveform description,
it expects the data to be read , the next cycle EP_READ is asserted. This will work if the FIFO produces data
in the very next cycle, when read and the address is presented. In most cases, where the FIFO is large and
the IPs introduce latencys > 0 , it becomes hard to pipeline and do a bulk read from the memories.
Especially if the USB buffering limits to 256 transactions during read, it fails.
If a user has an option to insert the needed latency numbers ( 1,2,3,) the buffered read will be more useful.
As a work around , implementing a WireIn ( to set the Address) and Wireout ( to read the data ) – and is as expected very slow for large memory dumps.
Appreciate a solution for this performance hit.