Implementation Issue When Migrating from XEM3001v2 to XEM7001

I am trying to move from XEM3001v2 to XEM7001, but am getting implementation issues in the Opal Kelly interface modules. The OK-related part of the code that is causing problems looks like this:

// Instantiate the okHostInterface and connect endpoints to
// the Opal Kelly Module Interface
okHostInterface     okHI    (   .hi_in(hi_in),

// Endpoint connections: HI to core and core to FPGA connections
// Wire In: Valid Address Range:  0x00-0x1F
okWireIn ep00(.ok1(ok1), .ok2(ok2), .ep_addr(Addr_WireInMsgCtrl), .ep_dataout(msg_ctrl));
okWireIn ep01(.ok1(ok1), .ok2(ok2), .ep_addr(Addr_WireInSignal), .ep_dataout(sw_in_signals));
okWireIn ep02(.ok1(ok1), .ok2(ok2), .ep_addr(Addr_WireInADC), .ep_dataout(sw_in_adc));
okWireIn ep03(.ok1(ok1), .ok2(ok2), .ep_addr(Addr_WireInPDM0), .ep_dataout(sw_in_pdm_0));
okWireIn ep04(.ok1(ok1), .ok2(ok2), .ep_addr(Addr_WireInPDM1), .ep_dataout(sw_in_pdm_1));
okWireIn ep05(.ok1(ok1), .ok2(ok2), .ep_addr(Addr_WireInPDM2), .ep_dataout(sw_in_pdm_2));
okWireIn ep06(.ok1(ok1), .ok2(ok2), .ep_addr(Addr_WireInPDM3), .ep_dataout(sw_in_pdm_3));

// Wire Out: Valid Address Range:  0x20-0x3F
okWireOut ep20 (.ok1(ok1), .ok2(ok2), .ep_addr(Addr_WireOutStatus), .ep_datain(msg_stat));
okWireOut ep21 (.ok1(ok1), .ok2(ok2), .ep_addr(Addr_WireOutSignal), .ep_datain(sw_out_signals));
okWireOut ep22 (.ok1(ok1), .ok2(ok2), .ep_addr(Addr_WireOutADC), .ep_datain(sw_out_adc));

// Trigger In:  Valid Address Range:  0x40-0x5F

// Trigger Out:  Valid Address Range:  0x60-0x7F

// Pipe In: Valid Address Range:  0x80-0x9F
okPipeIn ep80 (.ok1(ok1), .ok2(ok2), .ep_addr(Addr_PipeInScan), .ep_write(pipeI_write), .ep_dataout(pipeI_data));

// Pipe Out: Valid Address Range:  0xA0-0xBF
okPipeOut epA0 (.ok1(ok1), .ok2(ok2), .ep_addr(Addr_PipeOutScan),.ep_read(pipeO_read), .ep_datain(pipeO_data));

The first issue I found is that “name port connection ok2 doesn’t exist” on the okWireIn module, so I deleted those port connections. Now I am getting through synthesis and bump into the following error during implementation:

[DRC MDRV-1] Multiple Driver Nets: Net ep80/ has multiple drivers: ep80/GND/G, ep20/ok2[9]_INST_0/O, ep21/ok2[10]_INST_0/O, ep20/ok2[8]_INST_0/O, ep20/ok2[7]_INST_0/O, ep20/ok2[6]_INST_0/O, ep20/ok2[5]_INST_0/O, ep20/ok2[4]_INST_0/O, ep20/ok2[3]_INST_0/O, ep20/ok2[2]_INST_0/O, ep20/ok2[1]_INST_0/O, ep20/ok2[15]_INST_0/O, ep20/ok2[14]_INST_0/O, ep20/ok2[13]_INST_0/O, ep20/ok2[12]_INST_0/O… and (the first 15 of 65 listed).

I notice that “okWireOr” is not used anywhere, so I suspect this is related to the problem. What do I need to change? I am looking at the FrontPanel HDL documentation, but it is not specific enough to address this issue.

I have resolved this issue. Unlike on the XEM3001v2, the XEM7001 requires you to instantiate an “okWireOr” module to OR together the signals on the ok2 bus from each Opal Kelly module using that bus. The “Controls.v” sample file in the “Controls” example folder provides some working code for this.

Hope this helps someone in the future!