While this was simmering, I took care of other build errors and now it builds fine. Maybe the old error just didn’t clear. I closed and reopened the project and built it again and it builds ok.
For others trying this out, here are the things I ran across:
- Copy the sources and constraints to a new location. Be sure to add the OK*.v sources.
- You will probably be using a newer version of Vivado, so upgrade the fifo IP. (IP Sources tab, right click on each IP and select Upgrade)
- Go to IP catalog and add in Memory Interface Generator under Memories and Storage Units.
- Set up the MIG using the information in:
https://docs.opalkelly.com/display/XEM7310MT/DDR3+Memory
- complain about the random listing of pin names in the Xilinx interface…
- Add the MIG constraint files to the project.
- Change the name of the MIG instantiation in the top level Verilog file to match the name in the instantiation template (mig_7series_0.veo).
That seemed to work for me.