Ok… I see your point.
To clarify my intentions with the XEM6010: In my design the USB buss power will be passed through a smart switch current limiter and super cap charger to garantee no more than 500mA (or possibly less) is available to the device. The fpga configuration will not be to thirsty but will produce transient loads (High Speed Deserialisation and the like) possibly larger than 500mA scattered amoungst durations of idle time (where the XEM6010 load is reduced where possible). The average load will be below the USB2.0 limit - evened out by the large bucket (super cap with energy management harware and software fluff)
I have built a couple of prototypes with your XEM3005 and proved the concept and then I started reading the USB2.0 spec details before putting the XEM6010 project into copper and got bogged down with the USB power regulations…
Your XEM6010 consumes 117mA (when I measure it) without any config loaded in the FPGA. So the load is close enough to 1 unit load on power up which ticks the USB 2.0 spec.
If I limit the XEM6010 load to 500mA all should be ok on any host that can provide the high power spec. If the USB config bits don’t enumerate to a “high power device” (demands 5 unit loads) odd things are likely to occure on any unsuspecting low power USB2.0 port.
I’m wondering if it’s possible to alter the USB configuration in the Cypress chip or even just check to see what the config bits are after enumeration (regarding the power information). Is there an easy way to check this?
Am I wasting my time worrying?