XEM 6010 PLL Question

I read how the 3 PLL clocks to the FPGA can be setup or flashed thru FrontPanel. And how its sourced by a 48MHz clock from USB controller. Without seeing the 6010 schematic, can the FPGA setup the PLL (any control lines from FPGA to PLL?) If not what are the default frequencies of ClkA, ClkB, and ClkC to the FPGA if no PLL setup was performed, and are they reliable/repeatable? My question is because we do not plan to use USB port or FrontPanel, but we need predictable clocks for various FPGA builds. Thank You