VHDL sources



I am using the XEM3001-V2 and i need to interface a communication protocol to your host USB interface. To do this i need to understand the control signals of the “okHostInterface” component. Can anyone please post the .vhd files for the “okHostInterface”, “okwirein” and “okwireout” components ASAP, so that i can start developing my application.

Thanks and Regards,


The sources for the HDL modules are proprietary and not required to develop applications on the FrontPanel framework.



I need to interface my communication protocol with the host interface how i need to know how the timing diagram looks. Or can you give me a pointer on where to look for.




The FrontPanel framework provides wires, triggers, and pipes (see the FrontPanel User’s Manual) to your HDL design. You would then use these abstractions to build up the protocol to communicate.

The DESTester sample provides a good, albeit simple, example of a communication protocol using all three abstractions.


What is the transfer rate that you get from the FPGA to the host?

Can i get something in the range of 20 MB/s?



With FrontPanel 1.4.0, we achieve approx. 32MB/s from PC to FPGA.

As with any statistic, this requires some qualification. This is achieved in an application where we can stream directly to SDRAM. The SDRAM, therefore, acts as sort of a FIFO. This also assumes that the PC is not interrupted. PC’s are not real-time environments. They are subjected to all sorts of interruptions from mice, keyboards, hard drives, timers, internet packets, other USB events, screensavers, Windows Update, etc.

But, in very real applications, we have achieved this without too much effort. In fact, we give away an early version of our SDRAM controller that helps us. We use the internal block RAM as a staging cache for data to be paged out to SDRAM as it comes in. This allows us to run the USB interface (Pipes) at full throttle, for long transfers.

Our upcoming FrontPanel-3 release will be even better…


I read your post backwards. With FrontPanel 1.4.x, we get around 19.5MB/s from FPGA to host.

Again, big improvements will be seen with FrontPanel-3.


I read your post backwards. With FrontPanel 1.4.x,

HOW is it possipble to get such . its not working