Vhdl code error

VHDL / Verilog Discussion
1

this is the vhdl code i wrote:

architecture rtl of dff is
begin
clocked : process (AR,SR,SS,AS,CLK,EN)
variable Qint: std_logic;
begin
if AR=‘1’ then
Qint:=‘0’;
elsif AS=‘1’ then
Qint:=‘1’;
elsif rising_edge(clk) then
if SR=‘1’ then
Qint :=‘0’;
elsif SS=‘1’ then
Qint :=‘1’;
elsif EN=‘1’ then
Qint :=D;
end if;
Q

can anyone help me to find my mistake here?
thx

2

your missing an end if statement.

architecture rtl of dff is
begin
clocked : process (AR,SR,SS,AS,CLK,EN)
variable Qint: std_logic;
begin
[COLOR=“Red”]if AR=‘1’ then[/COLOR]
Qint:=‘0’;
elsif AS=‘1’ then
Qint:=‘1’;
elsif rising_edge(clk) then
[COLOR=“Red”]if SR=‘1’ then[/COLOR] [COLOR=“Red”]<= not Qint after tqn;
end process;
end rtl;