Urgent: Please Help with Verilog Code

VHDL / Verilog Discussion
1

I need help with my verilog code when trying to generate a random function. I have the following code:

module randnum(num);
	output [3:0] num;
	//integer number;
	reg [3:0] number;
	initial begin
		number = {$random} % 10;
	end
	assign num = number; 
endmodule

which gives me the following error:

ERROR:Xst:850 - "randnum.v" line 26: Unsupported System Function Call.

2

This is not a synthesizable call. You’ll need to build an appropriate random number generator in logic.