Hola… okay i’m having a really frustrating problem with timing and I’m running out of time. I’m designing a digital filter for an FPGA, but there are some hicups.
Basically, the filtering process contains a state machine with 20 states that all follow in straight forward sequence. I make use of megafunction multipliers and adders (LPM_MUL & LPM_ADD). One state will have one multiplication operation. then the output will be fed into an adder in the next state.
The problem im sitting with is that when i do a functional simulation, the results are correct. however, when i do a timing analysis, the values are incorrect. So I assume it’s a timing related problem. The only timing related warning I have is :
Warning: 31 (of 3893) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit’s timing constraints and clocking methodology, especially multicycles and gated clocks.
What exactly does this mean? How do I go about improving this. I’m stil a bit of a beginner with this language.
The other thing that I think might have a hand in the problem, is this:
Warning: Latch \p2:Temp_mem has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal present_state.s10
there are more than one of these. Could they be causing the delays or timing errors? I’ve seen some other posts on this topic but still don’t really grasp how I am suppose to fix it. The code in state S10 looks like this:
[B]next_state s unsafe behaviour is responsible and how the hell to fix it.
Thanks to anyone who responds