I’m planning a project that will require fast data acquisition from 32 sensor chips each via an SPI bus. I am a graduate student and am very new to embedded system design, but given my data throughput requirements (maximum estimated 7.32 MBps [58.59 Mbps]), it looks like the XEM6010-LX45 or LX150 will be suitable for my application.
Ideally, I would like to drive the 32 sensor chips synchronously with the same SCLK (master clock signal), and a separate clock or default active-low for SS (slave-select signal). I will then use ~64 of the 110 XEM6010 I/O ports for (MOSI, MISO). I am allowed to daisy-chain the sensor chips, which would reduce the number of SPI controllers needed, but driving the chips at higher frequencies (necessary for the same throughput as an all-master configuration) will increase the read-noise, which I would like to avoid if possible. Thus, I anticipate running 32 SPI master controllers on the FPGA. Does this sound reasonable?
For this application, where I am purely interested in reading the data as quickly as possible from the chips via USB (for high-level software access), what would the advantages of the LX45 versus LX150 be?