Yes, "\x00"16 means I should have 816 bit of data. So you are saying that if we request only 8*16 bit of data then the PipeOut should try to read only for 8 cycles?
Specifically what I’m trying (as a prototyping stage) is to have PipeOut read from FIFO output. In the test circuit I write a sequence of 16-bit wide number into FIFO like 0,1,2,3,4,5?.. and then have PipeOut read from it.
The result I got is instead 1,3,5,?. (there’s also another issue: it’s not always 1,3,5,… sometimes it becomes other things like 1,3,5,6 8,10?) So I think there’s a funny thing going on in the timing of the FIFO and the read.
The reason I said that I think EP_READ is on for 16 cycles is that I look at the last data_out from the FIFO after the PipeOut request has been carried out. From the sequence of data you now see that I always get double the number.
Another general question I always has is about clocking and timing.
For PipeOut, once you have EP_READ high, at the next clocking cycle, DATA has to be present. Is it a general practice to have the data (which you fetch from, for example, a FIFO) right at the clock edge or half the cycle before? Because I might think some data corruption might occur if the data is not fully stable at the clock.
I don’t know whether the question is clear? I will try again if you have trouble understanding.
Thank you very much!