Pipe endpoint to Xilinx pipe interface

Spartan-6 USB 2.0 Modules
1

I their an example out there of interfacing a pipeIn to a Xilinx generated fifo cell in verilog?

2

Yes. The RAMTester sample does this. The DESTester does a similar thing.

3

It’s true there are some examples, some coverage in the tutorials, and some coverage in the FrontPanel documentation of the PipeIn and PipeOut interface signals.

However, it takes a while, and some experimentation, to tease out the exact definition of the signals and their timing.

Could you add a list of signal definitions and timing sequence information to save user time?

Thanks

4

ot1 – The FrontPanel User’s Manual has a list of signal definitions and timing diagram for the pipes. Can you please explain what is not clear from these diagrams and we can take a look and try to clarify any confusion.

5

— Begin quote from Opal Kelly Support;3309

ot1 – The FrontPanel User’s Manual has a list of signal definitions and timing diagram for the pipes. Can you please explain what is not clear from these diagrams and we can take a look and try to clarify any confusion.

— End quote

Ah. I see that now. I guess I did not expect to find details on the hardware timing in a manual that has a software title!