Noob question with expecting endmodule error

Okay, I am just starting to program in verilog and I don’t understand this error at all. Can you help me?

Here is code:

module testingIf(in, out);
input [3:0] in;
output [3:0] out;

reg x[3:0];

assign x = 1'b0;

if(x[0] == 1'b0)
  x[0] t understand and I have tried everything I can think of. This is also a smaller example of what the larger problem is but the error is just the same.

Thank you for your time.