[QUOTE=czaiss;3466]Well I figured it out.
When I was converting the verilog to vhdl I misread the statement that set the chip select for the ram. I set it high instead of low.
Tested it after changing, now it works, the memory test application passed and i was able to run the hello world program on the ram.
If anyone needs a working example I could now provide one. Maybe Opal Kelly will host it on their download site.[/QUOTE]
Well I got microblaze to pass the memory test as well. It took me quite a while.
Here’s a quick run down of what I did.
I used BSB to build a microblaze core at 75mhz.
Peripherals are as follows:
- GPIO for leds
- GPIO for ddr2 cs# (MIG does NOT create this, took me a while to figure out)!
- ddr2 peripheral.
After that was done. I double clicked on the ddr2 guy to run the mig wizard. Selected ram, followed opal-kelly user manual for config options.
Next, GPIO for ddr2 was made into a 1 port GPIO, set to default output.
In the system.ucf I mapped the ddr2_gpio_pin to LOC=C3 (from ramtest example, this also took me a while to figure out) and added a pull down just in case.
So now we have our chip select pin (cs#) set to low on the proper pin, and we have a ddr2 peripheral.
One thing the auto tools will do is screw up the naming conventions.
Inside of edk you’ll see the external port names are something like MDDR2_dram_xxxx. However, the pin mapings made in MIG have names like mcbx_dram_xxx (go check the pins mappings, they are in /%projecet%/implementation/system_mcb_ddr2wrapper.ncf) (ncf is constraints file for memory, if you don’t see the file you’ll have to run generate net list first (even if net names are still screwed up)).
I’d recommend accepting the mig settings and updating the external port names inside edk (or the system.mhs file) to match.
If you don’t, when you go to synthesize, you’ll notice all your ram ports get trimmed.
So at this point you have pin net names mapped correctly to external ports (system.mhs matches ncf file), you have pull down on cs# line,now all you need is to fix the reference clock to match what you selected in BSB( i chose 200mhz). This is done via front panel.
Make your clock single ended in the system.ucf file and away you go.