Map error on okHI

Hi all,

Please help!!!
I got the following errors during map using xem6010 (xc6slx150-2fgg484) with or without read core on ISE 13.1, please help, it’s in urgent need to get a build done.
I am using the ngc files etc. from FrontPanel v4.0.5.

Many thanks.

ERROR:Pack:2811 - Directed packing was unable to obey the user design
constraints (BLKNM=okHI/core0okHI/core0/core0/a0/pc0/KCPSM6_SANDR) which
requires the combination of the symbols listed below to be packed into a
single SLICE component.

The directed pack was not possible because: One or more function generators
exclude the use of one or more register sites within the component. There are
more registers than can fit in the remaining available register sites.

The symbols involved are:
FLOP symbol
“okHI/core0/core0/a0/pc0/data_path_loop[6].low_hwbuild.shift_rotate_flop”
(Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_result)
FLOP symbol
“okHI/core0/core0/a0/pc0/data_path_loop[4].low_hwbuild.shift_rotate_flop”
(Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_result)
FLOP symbol
“okHI/core0/core0/a0/pc0/data_path_loop[2].low_hwbuild.shift_rotate_flop”
(Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_result)
FLOP symbol
“okHI/core0/core0/a0/pc0/data_path_loop[0].low_hwbuild.shift_rotate_flop”
(Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_result)
LUT symbol
“okHI/core0/core0/a0/pc0/data_path_loop[6].msb_shift_rotate.shift_rotate_lut_
O5” (Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_value)
LUT symbol
“okHI/core0/core0/a0/pc0/data_path_loop[4].mid_shift_rotate.shift_rotate_lut_
O5” (Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_value)
LUT symbol
“okHI/core0/core0/a0/pc0/data_path_loop[2].mid_shift_rotate.shift_rotate_lut_
O5” (Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_value)
LUT symbol
“okHI/core0/core0/a0/pc0/data_path_loop[0].lsb_shift_rotate.shift_rotate_lut_
O5” (Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_value)
LUT symbol
“okHI/core0/core0/a0/pc0/data_path_loop[6].msb_shift_rotate.shift_rotate_lut_
O6” (Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_value)
LUT symbol
“okHI/core0/core0/a0/pc0/data_path_loop[4].mid_shift_rotate.shift_rotate_lut_
O6” (Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_value)
LUT symbol
“okHI/core0/core0/a0/pc0/data_path_loop[2].mid_shift_rotate.shift_rotate_lut_
O6” (Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_value)
LUT symbol
“okHI/core0/core0/a0/pc0/data_path_loop[0].lsb_shift_rotate.shift_rotate_lut_
O6” (Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_value)
FLOP symbol
“okHI/core0/core0/a0/pc0/data_path_loop[7].low_hwbuild.shift_rotate_flop”
(Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_result)
FLOP symbol
“okHI/core0/core0/a0/pc0/data_path_loop[5].low_hwbuild.shift_rotate_flop”
(Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_result)
FLOP symbol
“okHI/core0/core0/a0/pc0/data_path_loop[3].low_hwbuild.shift_rotate_flop”
(Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_result)
FLOP symbol
“okHI/core0/core0/a0/pc0/data_path_loop[1].low_hwbuild.shift_rotate_flop”
(Output Signal = okHI/core0/core0/a0/pc0/shift_rotate_result)
ERROR:Pack:2811 - Directed packing was unable to obey the user design
constraints (BLKNM=okHI/core0okHI/core0/core0/a0/pc0/KCPSM6_CONTROL) which
requires the combination of the symbols listed below to be packed into a
single SLICEL component.

The directed pack was not possible because: One or more function generators
exclude the use of one or more register sites within the component. There are
more registers than can fit in the remaining available register sites.

The symbols involved are:
FLOP symbol “okHI/core0/core0/a0/pc0/run_flop” (Output Signal =
okHI/core0/core0/a0/pc0/run)
LUT symbol “okHI/core0/core0/a0/pc0/active_interrupt_lut_O6” (Output Signal
= okHI/core0/core0/a0/pc0/sx_addr4_value)
FLOP symbol “okHI/core0/core0/a0/pc0/t_state1_flop” (Output Signal =
okHI/core0/core0/a0/pc0/t_state)
FLOP symbol “okHI/core0/core0/a0/pc0/t_state2_flop” (Output Signal =
okHI/core0/core0/a0/pico_bram_enable)
XorCY symbol “okHI/core0/core0/a0/pc0/arith_carry_xorcy” (Output Signal =
okHI/core0/core0/a0/pc0/arith_carry_value)
FLOP symbol “okHI/core0/core0/a0/pc0/internal_reset_flop” (Output Signal =
okHI/core0/core0/a0/pc0/internal_reset)
FLOP symbol “okHI/core0/core0/a0/pc0/arith_carry_flop” (Output Signal =
okHI/core0/core0/a0/pc0/arith_carry)
LUT symbol “okHI/core0/core0/a0/pc0/reset_lut_O5” (Output Signal =
okHI/core0/core0/a0/pc0/run_value)
LUT symbol “okHI/core0/core0/a0/pc0/reset_lut_O6” (Output Signal =
okHI/core0/core0/a0/pc0/internal_reset_value)
LUT symbol “okHI/core0/core0/a0/pc0/t_state_lut_O5” (Output Signal =
okHI/core0/core0/a0/pc0/t_state_value)
LUT symbol “okHI/core0/core0/a0/pc0/t_state_lut_O6” (Output Signal =
okHI/core0/core0/a0/pc0/t_state_value)
FLOP symbol “okHI/core0/core0/a0/pc0/sx_addr4_flop” (Output Signal =
okHI/core0/core0/a0/pc0/sx_addr)

Are you able to build our samples?

I never had this issue before changing to Synplify Premier with ISE 13.1. Could build everything with Synplify Pro+ISE 13.1. Also tried going back a Frontpanel version, but with the same failure.

dkong,
are you using Synplify or directly ISE?

Thanks.

Synplify Premier enhanced optimization can create illegal mapping (more or less, depending on the version). To avoid the problem one can turn enhanced optimization off by adding this line in the project file:

set_option -enhanced_optimization 0

Regards,
Ralf