According to the UCF file, the flash pins are connected as follows:
I am surprised to see flash_clk called out explicitly. I would expect it to be connected to CCLK. Are some of the flash signals connected to multiple FPGA pins so they can be used both for configuration and after configuration? I thought I would have to instantiate the STARTUP_SPARTAN6 module to provide access to CCLK (similar to XAPP1020), but I guess this would make it simpler.
But more importantly, I can’t find any documentation that specifies the direction of the flash_din and flash_dout signals. Are the din/dout directions from the perspective of the flash chip, or the FPGA?
Thanks for any info.