LVDS on JP2/JP3

The XEM6010 users manual states “Finally, for pins routed to differential pair I/Os on the FPGA, the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs” of JP2 & JP3. Can you provide any more information on what the length matching tolerance is and if they are impedance matched? Basically, can these be used for LVDS I/O in the 250MHz range?

Thanks,
Aaron

Aaron–

Yes, the routes are impedance-controlled to 50-ohm single-ended. This is approximately 100-ohm differential on these boards.

The lengths are provided as exact measurements, so length tolerance is very small due to process variation. On the order of tens of microns or less.

To directly answer your question, though, the routes should work just fine for 250 MHz LVDS.

Xilinx says (ref 1) that 2.5V and 3.3V LVDS outputs are only available on I/O banks 0 and 2. From my spot check of the pins connected to JP2 and JP3 on the XEM6010, it looks like only I/O bank 1 is available for user I/O. Am I correct in concluding that LVDS_25 and LVDS_33 output is unavailable on the XEM6010?

thanks,
James

ref 1: (


page 28)

Most of JP3 is bank 0. (See the suffix of the pins in the XEM6010 User’s Manual, page 23)

Aha, thank you very much for the correction.

James