LVDS_33 on XEM6010

According to the Spartan-6 FPGA SelectIO Resources User Guide, it is possible to use LVDS_33 I/O on Bank 0 with VCCO set to +3.3V.

However, the XEM6010 user manual states:
[INDENT]“In order to use differential I/O standards with the Spartan-6, you must set the VCCO voltages for the appropriate banks to 2.5v according to the Xilinx Spartan-6 datasheet.”[/INDENT]

Is the XEM6010 manual incorrect? Or is there a reason why the XEM6010 does not support LVDS_33?




Follow the Xilinx documentation. We’ll need to review the implications and see what is allowed.

The Spartan-3 generation only allowed LVDS in one direction (I forget which) when 3.3v was applied. It’s possible that Xilinx changed their documentation and supported capabilities after the XEM6010 was designed and the documentation written. We’ll take a look.