Kindly explain difference in Verilog code mentioned below?

VHDL / Verilog Discussion
1

Can anyone explain the diff between these 2 codes. The first one creates Clock while other

generates straight line. Why

module osc2 (clk);
output clk;
reg clk;
initial
#10 clk = 0;
always @(clk)
#10 clk <= ~clk;
endmodule

module osc2 (clk);
output clk;
reg clk;
initial
#10 clk = 0;
always @(clk)
#10 clk = ~clk;
endmodule

The only difference in codes is that one uses blocking and other non blocking assignment.

2

That’s interesting. I would guess it is because you’re making a delayed assignment (#10 …) on an event basis (always @clk) that is dependent upon the delay. It ends up chasing itself. You may even have tiny glitches on the clock at regular intervals if you zoom in far enough.

I usually make a clock with:

always #5 clk = ~clk;

There’s no reason to trigger the always block on an clk event.