I think there is an error in the XEM6010-UM pinout on the datasheet

JP2 pin 48, if it goes to R22 like specified, should be connected to FPGA pin IO_L49N_1. In the datasheet it says L59N_1.

Unfortunately, this makes me question JP3 41 and 43 connected to bank 1 in the middle of so many Bank 0 connections. But I suppose I’ll have to give you the benefit of the doubt there.




Thank you for pointing out this typo. You are correct. It should be “L49N_1”. All other pairs follow the same convention (P, N).

JP3 41, 43 are correct as published.