JP2 pin 48, if it goes to R22 like specified, should be connected to FPGA pin IO_L49N_1. In the datasheet it says L59N_1.
Unfortunately, this makes me question JP3 41 and 43 connected to bank 1 in the middle of so many Bank 0 connections. But I suppose I’ll have to give you the benefit of the doubt there.
Matt
http://www.xilinx.com/support/packagefiles/s6packages/6slx45fgg484pkg.txt