FIFO core generator error

Spartan-6 USB 2.0 Modules
1

Good afternoon,

I was trying to generate a FIFO like suggested using ISE software, I have included the .xco file in the project and had included the component generated in my .vhd

fifo0 : fifo_generator_v8_1 PORT MAP (
clk => clk,
rst => rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
wr_ack => wr_ack,
empty => empty,
valid => valid,
data_count => data_count,
prog_full => prog_full
);

Unfortunately I get these 2 warnings:

WARNING:Xst:1814 - Core does not contain any logic.
WARNING:Xst:2957 - There are clock and non-clock loads on clock signal hi_in_0_IBUFG_BUFG. This is not a recommended design practice, that may cause excessive delay, skew or unroutable situations.

and while running the Implement Design I get en error:

ERROR:NgdBuild:604 - logical block ‘fifo0’ with type ‘fifo_generator_v8_1’ could
not be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, case mismatch between the block name and the edif or ngc file name, or
the misspelling of a type name. Symbol ‘fifo_generator_v8_1’ is not supported
in target ‘spartan6’.
Can anybody help me please…
Thanking you in advance,
Nanou

2

nanou-- This sounds like a question that may be better suited to the folks at Xilinx. Have you submitted a WebCase?

Although, I will mention that we use cores on a consistent basis and errors like this are typically indicative of a typo or other error on our end.

3

I found the problem, I had to put in the same folder than my project the files generated by the core, after closing and reopening the ISE, it works now.

However I get this warning and I don’t know if you can help me on this. I am using a 800KHz clock derived from the hi_in(0).

WARNING:Xst:2957 - There are clock and non-clock loads on clock signal hi_in_0_IBUFG_BUFG. This is not a recommended design practice, that may cause excessive delay, skew or unroutable situations.

Thank you,

Nanou

4

Nanou–

The warning pretty much says it all. What you’re doing isn’t a recommended design practice, but it’s allowed.