Dividision by repeted multiplication

VHDL / Verilog Discussion
1

Hi everyone,
Did everybody ever did the division by repeated multiplication algorithm in VHDL code??
I have this as my project, since im beginer in this fields and was running out of time, if there’s anyone out there ever did this kind of project please help me. I will be so very thankfull by this. really.

we can discuss further by contact me at: [email protected]

looking forward to your helps (it will be reward as my apreciate of your help, if you dont mind)…

Thanks,
Regards,
Steve.

2

You can use any one of the several division modules in Xilinx’s core generator. That is if you do not have to write one yourself.

3

— Begin quote from phil126;1880

You can use any one of the several division modules in Xilinx’s core generator. That is if you do not have to write one yourself.

— End quote

I prefer to write it manualy (actualy). If there’s anyone ever did this kind of project please help me.
contact me: [email protected]

Thanks,
Regards,
Steve.