Xilinx WebPACK 10.1 problem?


I am having problems generating program files in Xilinx WebPACK 10.1. The program files I generate do not work when I load them into the FPGA using FrontPanel.

My setup is as follows:
Ubuntu 8.04
Xilinx XEM3001v2 with f/w 3.0
FrontPanel-3.0-FC5 (the FC7 version would not work with Ubuntu 8.04)
Xilinx WebPACK ISE 10.1

I know it’s not my VHDL code because when I generate the bit file from another computer, it works. This is the setup for the computer that generates a working bit file:
Windows XP SP2
FrontPanel 3.0
Xilinx WebPACK ISE 9.2i

I am using the exact same project settings in both cases. Simulations of my code using Xilinx simulator (as well as ModelSim on the Windows PC) works fine on both computers. Also, if I use the 10.1 generated bit file and program the opal kelly board using FP 3.0 on a windows pc, it still does not work. When I take the bit file generated from 9.2i on a windows pc and program the board using FP 3.0 on the linux computer, the board works fine. Thus it’s only generating programming file on my linux setup that has a problem…

So my questions are:

  1. Has anyone tried using Xilinx ISE 10.1 on a computer running Windows XP to generate bit files?
  2. Is anyone having this problem on a linux system w/ Xilinx ISE 10.1 (or 9.x versions?)

Thanks in advance!


I have generated bitfiles on a system with Windows XP SP2, ISE 10.1 (with service pack) and loaded them from Matlab via the Front Panel API. They worked fine.

I did have a problem with ISE 10.1 before I installed the Service Pack, but I don’t recall what the symptoms were.