I assume sys_clk4 and sys_clk5, mentioned in the UCF file, are undedicated general purpose signals that just go from the FPGA to the expansion connectors. In the UCF file they are listed as FPGA pins U12 and T14. In the XEM6310 User’s Manual, table on page 18, it says JP2-11, the former sys_clk4 in the XEM6010, is FPGA U22. I believe this should read U12, not U22.
Also, there is a new “reset” signal in the UCF file (Pin AB8). Since there is no pushbutton on the board I assume this is a power-on reset issued during the new Reset Profiles, and that it’s active high?
One other minor nit: the UCF file has the I/O standard for the sys_clkp and sys_clkn pins as LVDS_33. In at least one of the samples (destop.vhd) the VHDL generic says LDVS_25. It really doesn’t matter for LVDS inputs (LVDS is LVDS, no matter what the supply is), but to avoid confusion (and Xilinx errors) these should be the same. But I’m confused as to what the bank voltage really is:
Page 12 of the manual says " … cathodes wired directly to the FPGA on Bank 2 with a bank I/O voltage of 3.3v."
Page 15 of the manual says " … are attached to FPGA Bank 2 which is powered as a 1.8v bank". Repeated on Page 16. Also table on Page 18.
Which is it?
( I’m pretty sure the answer is 1.8V since the okHU, okUH, etc. signals have LVCMOS18 in the UCF file and they are in Bank 2 as well. )
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I assume sys_clk4 and sys_clk5, mentioned in the UCF file, are undedicated general purpose signals that just go from the FPGA to the expansion connectors. In the UCF file they are listed as FPGA pins U12 and T14. In the XEM6310 User’s Manual, table on page 18, it says JP2-11, the former sys_clk4 in the XEM6010, is FPGA U22. I believe this should read U12, not U22.
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Yes. This is correct. We will make the change to the documentation. Thank you for pointing this out.
[QUOTE=jadwin79;3848]
Also, there is a new “reset” signal in the UCF file (Pin AB8). Since there is no pushbutton on the board I assume this is a power-on reset issued during the new Reset Profiles, and that it’s active high?[/QUOTE]
Yes. This is also correct. We have added some language to the XEM6310 User’s Manual to mention this signal. Thanks again!
— Begin quote from jadwin79;3849
One other minor nit: the UCF file has the I/O standard for the sys_clkp and sys_clkn pins as LVDS_33. In at least one of the samples (destop.vhd) the VHDL generic says LDVS_25. It really doesn’t matter for LVDS inputs (LVDS is LVDS, no matter what the supply is), but to avoid confusion (and Xilinx errors) these should be the same. But
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We’ll take a look and adjust these to resolve any inconsistencies. Thank you for pointing them out.
This is incorrect. The Bank I/O voltage is, indeed, 1.8v and we have updated the documenation to reflect this. Again, thank you for pointing it out.