I assume sys_clk4 and sys_clk5, mentioned in the UCF file, are undedicated general purpose signals that just go from the FPGA to the expansion connectors. In the UCF file they are listed as FPGA pins U12 and T14. In the XEM6310 User’s Manual, table on page 18, it says JP2-11, the former sys_clk4 in the XEM6010, is FPGA U22. I believe this should read U12, not U22.
Also, there is a new “reset” signal in the UCF file (Pin AB8). Since there is no pushbutton on the board I assume this is a power-on reset issued during the new Reset Profiles, and that it’s active high?