Hi guys!
I am trying to generate the bit file of the code that Opal Kelly have supplied to me, about DDR2 ram and it is not working! It always gives constraint errors and some of the files are MISSING, and no matter what I could not handle the memory interface generator. I would like to use and test RAMTester however there are some missing files such as init_mem_pattern_p0 and m_traffic_gen_p0. As a result, I could not integrate the code as a whole, and make changes. There is not enough information provided, so I could not achieve anything due to lack of information!
This is soooo urgent, so I appreciate if you can answer as soon as possible 
Thanks in advance,
Best wishes,
Sevgi Gökce Kafali
The samples are provided as a reference. You should use our sample code, but generate the MIG files yourself. The MIG is regularly updated by newer versions of the Xilinx tools and it’s best to use the most recent version of the files.
Any new information on this? I went with the opal kelly xem6310 because it had the RAM I needed. I expected that included working HDL/API example. I was surprised to get errors when I tried to build it. I went into MIG and there are a lot of options that aren’t listed in the short um blurb. I can probably blunder through it but it’s an engineering effort I was hoping to avoid by purchasing this board.
Is there an updated RAMTester that works with ISE14.7 (latest version released in 10/2013)?
The RAMTester we provide works with ISE 14.7. But you still need to build the MIG through the Xilinx tool. What errors do you get? Please note that the MIG is provided by Xilinx. If you’re having errors building it, then you really need to reach out to Xilinx for support there – we don’t support the ISE or Vivado tools and certainly couldn’t address any bugs in them. But we’re not aware of any issues.
I understand that the MIG is provided by Xilinx and I wouldn’t (and didn’t) ask you to resolve their problems. I’m talking about problems out of the box with the Opal Kelly RAMTester example on the XEM6310 board.
The first error is the fifo was built for a different spartan part. The .xco file is there so that is easy to recreate. Sort of makes you think that this has never been tested with the XEM6310.
The MIG is much harder. There are many more parameters and the ports have different names with the current version of MIG. I’m dissappointed that an up to date example isn’t provided by OK to get started with. Like I said, this release of ISE and MIG are 3 years old.
Which XEM6310 are you using? I just quickly built up the RAMTester sample for the -LX45 and ran into zero issues using the included MIG.
All samples are tested prior to release.
EDIT: Also, please ensure that you aren’t including the “example_top.v” and “example_top.ucf” files in the MIG sample folder. These are hold-overs from the MIG from Xilinx and aren’t necessary for the RAMTester sample.
Hi Tom,
Great. Can OK update this example to ISE 14.7 and test it on the xem6310 board?
Thanks
That was using ISE 14.7 and the XEM6310-LX45, I even ran the tests and they passed just fine.
Sometimes users find that if they re-create the project from scratch it will build okay, there are occasionally settings that were missed along the way that lead to errors in the project preventing it from building.
If you are still having issues this might be something better suited to email support, just send a message to [email protected] to open a ticket.