XEM5010 - RAMTest and Available address space on DDR memory

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1

In reviewing the RAMtest example and the documentation, I am trying to reconcile a difference I am seeing.

RAMtest example in both the verilog and .ucf reference a 10 bit CAS and 13 bit RAS address space.

If the device has 128MB available, what bit/register combination makes up the 27 bits need to represent this data space?

I’ve modified the simulation to run over the 128MB range claimed in the documentation. I get the following error:

[FONT=“Courier New”]tb.mem0.memory_write: at time 94243100.0 ps ERROR: Memory overflow. Write to Address 000400 with Data xxxxxxxxxxxxxxxx177b96f51fe5f579 will be lost.
You must increase the MEM_BITS parameter or define MAX_MEM.
/home/pmeyer/WORK/Intersil/dev/OpalKelly/sim/ramtest/ddr2_model/ddr2.v:477 if (STOP_ON_ERROR) $stop(0);
[/FONT]

Thoughts? :confused:

2

FYI. Looking a the simulation, the error occurs when the DDR2 model gets ras_n strobed with address 8 and then cas_n the sequence of addresses: 0, 4, 8, C.

Peter

3

Peter–

I’m not sure I completely follow your post, but I’ll refer you to the Micron datasheet for a bit more detail.

The 64Mx16 device is covered by A0-A12 row addresses, A0-A9 column addresses, and BA0-BA2 bank addresses. Since the device is x16, you cannot address a single byte without applying the lower/upper data strobes.

So perhaps your 27 total comes from: 13 row addresses, 10 column addresses, 3 bank addresses, and the “address” achieved by the lower/upper data strobe?

But I’ll also note (if it’s not clear to DDR2 newcomers) that reading/writing DDR2 through the Xilinx MIG DDR2 controller is done in “batches” of multiple words that are queued through a combination of command/data FIFOs. It’s a long way from the more comfortable SRAM reads/writes.

4

Administrator:

Thanks for replying.

I am using the MIG controller and am pushing in batch writes of 4x32 words. When I get an error from the ddr2.v model as stated earlier, the RAS has strobed in 0x8 and the CAS addressing is back to 0x00, and onwards by 0x4.

My error may be with the ddr2.v model and not having the parameter set to it correctly. Can you comment?

Peter

5

I think I better understand…

64M x 16 is 8M x (4 long word burst). According to the README, the MEM_BITS defines the number of “4 long word burst” locations available.

Technically, the RAMtest run file should have included: -GMEM_BITS=23 to reflect the full memory space available on the XEM5010.

Thoughts?

Peter