In reviewing the RAMtest example and the documentation, I am trying to reconcile a difference I am seeing.
RAMtest example in both the verilog and .ucf reference a 10 bit CAS and 13 bit RAS address space.
If the device has 128MB available, what bit/register combination makes up the 27 bits need to represent this data space?
I’ve modified the simulation to run over the 128MB range claimed in the documentation. I get the following error:
[FONT=“Courier New”]tb.mem0.memory_write: at time 94243100.0 ps ERROR: Memory overflow. Write to Address 000400 with Data xxxxxxxxxxxxxxxx177b96f51fe5f579 will be lost.
You must increase the MEM_BITS parameter or define MAX_MEM.
/home/pmeyer/WORK/Intersil/dev/OpalKelly/sim/ramtest/ddr2_model/ddr2.v:477 if (STOP_ON_ERROR) $stop(0);