XEM3050 - RAMtest virtex5 does not support tri-state buffers

#1

I am trying to regenerate the sample RAMtest.

During build, the Xilinx ISE tool reports back that several ok modules can not be implemented as they contain tri-states. Here is a sample of the error log.

-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
ERROR:MapLib:824 - Tri-state buffers are not supported in Virtex5. Block ok2
must be removed from the design.
WARNING:MapLib:35 - Mapper failed to process logical block ep00/ok2. Please
refer to previous error/warning message(s) to identify the problem.
ERROR:MapLib:824 - Tri-state buffers are not supported in Virtex5. Block ok2
must be removed from the design.
WARNING:MapLib:35 - Mapper failed to process logical block ep00/ok2. Please
refer to previous error/warning message(s) to identify the problem.
ERROR:MapLib:824 - Tri-state buffers are not supported in Virtex5. Block ok2
must be removed from the design.

-=-=-=-=-=-=-=-=-=-=–=-=-
I have tried:
instanciating: okHostInterface_xem5010 in place of okHostInterface in the ramtest.v file.

It seems as if the okLibrary.v file need to be updated or modified to deal with the Virtex5 constraint.

Any thoughts?

Peter

#2

@Peter- Can you post a few lines of your HDL that include the instantiation of the okHost and other items?

#3

Also – your post is titled “XEM3050…” but the XEM3050 is not a Virtex-5 device. Are you using the XEM5010?

#4

This is my bad. I am building for a XEM5010, but pulled my example from the XEM3050-Verilog directory.

I have installed the FrontPanel-FC10-3.0.11 version of the FrontPanel.

Not knowing enough about the design of the ok modules, can I get a pointer?

Thx!!

#5

A more general comment is if I can get example code for the XEM5010 for all the sample examples.

Many thank!!

#6

I am looking in the FrontPanel 3.1 release and also see and addenum for the 5010 device.

#7

@Peter-

Yep, that’s where you want to look.
http://forums.opalkelly.com/showthread.php?t=876

The release info and samples should explain it all.

#8

The FrontPanel3.1 release has what I needed to build a .bit file. Many thanks!!

I’ve also just posted a request for ModelSim 6.4b compatible libraries. This version is the only one currently available from the Xilinx website. I also ask in the post if you could instead create simulator agnostic encrypted verilog models.