XEM3001 firmware


#1

The XEM3001 firmware set, does it allow controlling pins on the FGPA w. data from USB at the “same time” as returning data measured on the FPGA over USB to the PC, WITHOUT any significant delays between “bytes” etc communicated over USB? I am very intersted in performance in this respect.


#2

The API and firmware just provide a means by which to communicate between the FPGA and the host PC. How you capture or output data on the FPGA pins is up to you.

For example, if you want to assert levels on certain pins and capture levels on other pins simultaneously (on a clock edge, for example), then one way to do that would be to have the host send a Trigger In to the FPGA. The FPGA would then perform the action on this trigger. At some other time, you could read out the levels captured on those pins.

Does this make sense? Is there more to your question?


#3

[QUOTE=Jake]The API and firmware just provide a means by which to communicate between the FPGA and the host PC. How you capture or output data on the FPGA pins is up to you.



Does this make sense? Is there more to your question?[/QUOTE]

Lets say I generate 10GB data in the PC that I want to stream out trough 8 digital output signals of the FPGA - as fast as possible. Now, this is not difficult to do with the FPGA itself. The question is really, how effecient is the PC-FPGA transfer for large amounts of data?

Also, while sending data, I also want to measure “return values”, that are similarly tranferred back to the PC via USB.

These two data streams are active simultaneosly.

Can your firmware handle this sitauation… with almost no delay transfer data between PCFPGA (except what is caused by the USB bus itself).

-nets


#4

How much data is being “returned” to the PC? How fast, how often? Is it regular (i.e. every 1024 bytes of PC->FPGA data) ?


#5

— Begin quote from Jake

How much data is being “returned” to the PC? How fast, how often? Is it regular (i.e. every 1024 bytes of PC->FPGA data) ?

— End quote

10GB out 10GB in…

-nets


#6

— Begin quote from Jake

How much data is being “returned” to the PC? How fast, how often? Is it regular (i.e. every 1024 bytes of PC->FPGA data) ?

— End quote

10GB out 10GB in… as fast as possible. Always same amount out and in.

-nets


#7

Best case we’ve seen is around 18MB/s on a Linux build. (Pentium 4 2.4GHz, Shuttle SB51G motherboard)

You’ll need to alternate in/out:

PC->FPGA WriteToPipeIn(1024kBytes)
FPGA->PC ReadFromPipeOut(1024kBytes)

The ‘chunk size’ should be as large as possible to minimize overhead and boost rates.

Jake


#8

Ok - thanks!

I will look into the USB protocol.

-nets