Is there any way to specify the initial value that the wireIn endpoint will have? I believe this is currently set to all 0’s, but I have an active low signal that I would like to avoid asserting until other configuration steps in my system have taken place and I’d like to initialize some of the bits in the wireIn to 1. I am using the wireIn as control signals that are mapped directly to the output pins of the FPGA.
If there isn’t currently a way to do this, I can work around it, but it would be a nice feature to have.