I have been reading the FrontPanel UM and have noticed the latency of the wire|trigger transactions is roughly 1 millisecond (plus or minus).
One type of access that I need to the device is basically programmed IO. I need to read and write several 16-bit registers each millisecond. It varies, but for example lets just say I need to perform 8 register writes and 64 register reads each millisecond. All registers are 16-bits.
I understand that the latency on the USB is not gauranteed, and that this really won’t work. But I am actually just using the FPGA to simulate the real design. So in my “simulation” I will gate the clock to turn it off and allow the software to keep up. But I would like my “simulation” to run as fast as possible.
I understand that the pipes are faster for bulk transfer, but that they have more setup overhead.
So here is my question:
Has someone determined the crossover point (in bytes for example) from wire|trigger to pipe?
In other words, can we say that for less than “X” bytes wire|trigger is the fastest due to less overhead? And for greater than “X” bytes pipe is the fastest due to burst?