Windows 7 bluescreen issues

Hello. I’m using your XEM6110-LX45 to make control signals for my CMOS image sensor
which was designed from my laboratory and fabricated from fabrication company.
The goal is to get image from the sensor to my MFC program.

But every time, I get all kinds of bluescreen error some time after getting the image.

the kinds are:
Windows Driver Framework
BAD_POOL_CALLER
PAGE_FAULT_IN_NONPAGED_AREA
IRQL_NOT_LESS_OR_EQUAL
and more…

the funny thing is that the error is random and changes every time.
so I was wondering if your Windows 7 Driver is somewhat unstable.
If I downgrade my OS to Windows XP, will this issue go away?

Do you have a recommended developing system?

The driver version is 0.9.0.6. Do you perhaps have a newer version?

My system is:

               Intel i3 540
               Gigabyte GA-H55M-S2V(using on-chip video)
               4G DDR3 RAM

We have used our driver quite a bit since the initial release with no problems. However, you do need to make sure your software is stable – we cannot control that.

We would suggest making sure that your software does not crash and, if it does terminate unexpectedly that it close all handles to the driver. If a transfer is in progress, the driver will have open memory pools and/or DMA transfers in process.

Have the bluescreens been related to instances when your software terminates unexpectedly? Have you encountered any such problems using our samples or FrontPanel?

I’m having bluescreen issues as well, but this is with the demo code.

  1. I resynthesized and implemented the “first.v” project in Xilinx ISE 13.2, and that worked fine. I was able to make minor changes to the LEDs and route in the external clock and that works ok. I also was able to use my C# application to replicate the FrontPanel behavior. So far, so good.

  2. I then tried the ‘pipetest’ demo, using the original *.exe and *.bit file and that works fine.

  3. I then created a new project and tried to synthesize/implement the pipetest sample code. I used the original files (the pipetest.v, pipe_in_check.v and pipe_out_check.v and the pipetest\XEM6110-Verilog\xem6110.ucf, together with all the library core files okLibrary.v, etc) with the same project settings I used for the first.v demo. After it is built, I then run the prebuilt pipetest.exe and it blue screens. In other words, I’m using only source files supplied by OK, and it’s not working.

Can you send me a Xilinx ISE 13.2 project (with all the verilog files, so all I have to do is rebuild it) that is known to work with pipetest? If you want, I can post my project as well.

Not sure if this helps, but here it is:

WARNING:HDLCompiler:1127 - “C:\gener8\qualcomm\rotdisp\trunk\blade_driver_ok\XEM6110\okLibrary.v” Line 57: Assignment to dcm_CLK0_OUT ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - “C:\Program Files\Opal Kelly\FrontPanelPCI\Samples\PipeTest\XEM6110-Verilog\PipeTest.v” Line 72: Assignment to pipe_in_done ignored, since the identifier is never used
WARNING:NgdBuild:443 - SFF primitive ‘host/core0/core0/a0/pc0/read_strobe_flop’
has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
‘host/core0/core0/a0/pc0/k_write_strobe_flop’ has unconnected output pin
WARNING:NgdBuild:440 - FF primitive ‘host/core0/core0/a0/pc0/interrupt_ack_flop’
has unconnected output pin
WARNING:MapLib:701 - Signal okGH connected to top level port okGH has
been removed.
WARNING:MapLib:701 - Signal okGH connected to top level port okGH has
been removed.
WARNING:Place:838 - An IO Bus with more than one IO standard is found.
Components associated with this bus are as follows:
Comp: okGH IOSTANDARD = DIFF_SSTL18_I
Comp: okGH IOSTANDARD = DIFF_SSTL18_I
Comp: okGH IOSTANDARD = DIFF_SSTL18_I
Comp: okGH IOSTANDARD = DIFF_SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = LVCMOS18
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
Comp: okGH IOSTANDARD = SSTL18_I
WARNING:Place:838 - An IO Bus with more than one IO standard is found.
Components associated with this bus are as follows:
Comp: okHG IOSTANDARD = DIFF_SSTL18_I
Comp: okHG IOSTANDARD = DIFF_SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = SSTL18_I
Comp: okHG IOSTANDARD = LVCMOS18
Comp: okHG IOSTANDARD = LVCMOS18
Comp: okHG IOSTANDARD = LVCMOS18
Comp: okHG IOSTANDARD = LVCMOS18
WARNING:Par:288 - The signal host/core0/core0/a0/cb0/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal host/core0/core0/a0/cb0/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route
this signal.
WARNING:Route:522 - Unusually high hold time violation detected among 1 connections.The router will continue and try to fix it
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:PhysDesignRules:367 - The signal
is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
host/core0/core0/lbi_0/ser_0/tdpram_0/BU2/U0/blk_mem_generator/valid.cstr/ram
loop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram) port(s) with READ_FIRST mode
has certain restrictions. Make sure that there is no address collision. A
read/write on one port and a write operation from the other port at the same
address is not allowed. RAMB16BWER, when both ports are 18 bits wide or
smaller, A13-6 including A4 cannot be same. When any one port is 36 bits
wide, A13-7 including A5 cannot be the same. Violating this restriction may
result in the incorrect operation of the BRAM.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
host/core0/core0/lbi_0/ser_0/tdpram_0/BU2/U0/blk_mem_generator/valid.cstr/ram
loop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram) port(s) with READ_FIRST mode
has certain restrictions. Make sure that there is no address collision. A
read/write on one port and a write operation from the other port at the same
address is not allowed. RAMB16BWER, when both ports are 18 bits wide or
smaller, A13-6 including A4 cannot be same. When any one port is 36 bits
wide, A13-7 including A5 cannot be the same. Violating this restriction may
result in the incorrect operation of the BRAM.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
host/core0/core0/lbi_0/des_0/tdpram_0/BU2/U0/blk_mem_generator/valid.cstr/ram
loop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram) port(s) with READ_FIRST mode
has certain restrictions. Make sure that there is no address collision. A
read/write on one port and a write operation from the other port at the same
address is not allowed. RAMB16BWER, when both ports are 18 bits wide or
smaller, A13-6 including A4 cannot be same. When any one port is 36 bits
wide, A13-7 including A5 cannot be the same. Violating this restriction may
result in the incorrect operation of the BRAM.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
host/core0/core0/lbi_0/des_0/tdpram_0/BU2/U0/blk_mem_generator/valid.cstr/ram
loop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram) port(s) with READ_FIRST mode
has certain restrictions. Make sure that there is no address collision. A
read/write on one port and a write operation from the other port at the same
address is not allowed. RAMB16BWER, when both ports are 18 bits wide or
smaller, A13-6 including A4 cannot be same. When any one port is 36 bits
wide, A13-7 including A5 cannot be the same. Violating this restriction may
result in the incorrect operation of the BRAM.

[ATTACH]228[/ATTACH]Attached are the timing failures. There are 7 failed paths, but only 1 looks relevant because the rest are DDR2 related:

[FONT=“Courier New”]Hold Paths: COMP “okGH” OFFSET = IN 2 ns VALID 2.7 ns BEFORE COMP “okGH” HIGH;

Paths for end point host/core0/core0/lbi_0/prdr_0/async_d (SLICE_X8Y11.DX), 1 path

Slack (hold path): -1.755ns (requirement - (clock path + clock arrival + uncertainty - data path))
Source: okGH (PAD)
Destination: host/core0/core0/lbi_0/prdr_0/async_d (FF)
Destination Clock: okHE rising at 0.000ns
Requirement: 0.700ns
Data Path Delay: 4.066ns (Levels of Logic = 1)
Clock Path Delay: 6.015ns (Levels of Logic = 3)
Clock Uncertainty: 0.506ns

Clock Uncertainty: 0.506ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.195ns
Phase Error (PE): 0.405ns

Minimum Data Path at Slow Process Corner: okGH to host/core0/core0/lbi_0/prdr_0/async_d
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
AA2.I Tiopi 0.987 okGH
okGH
okGH_26_IBUF
ProtoComp272.IMUX.20
SLICE_X8Y11.DX net (fanout=1) 3.172 okGH_26_IBUF
SLICE_X8Y11.CLK Tckdi (-Th) 0.093 host/core0/core0/lbi_0/prdr_0/async_d
host/core0/core0/lbi_0/prdr_0/async_d
------------------------------------------------- ---------------------------
Total 4.066ns (0.894ns logic, 3.172ns route)
(22.0% logic, 78.0% route)

Maximum Clock Path at Slow Process Corner: okGH to host/core0/core0/lbi_0/prdr_0/async_d
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
Y13.I Tiopi 1.187 okGH
okGH
host/pll_buf_0/IBUFDS
ProtoComp270.IMUX
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 6.243 host/pll_clkin1
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.873 host/pll_base_inst/PLL_ADV
host/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.482 host/pll_clkout0
BUFGMUX_X3Y13.O Tgi0o 0.209 host/pll_buf_2
host/pll_buf_2
SLICE_X8Y11.CLK net (fanout=1010) 1.767 okHE
------------------------------------------------- ---------------------------
Total 6.015ns (-2.477ns logic, 8.492ns route)
[/FONT]


PipeTest.twx.zip (15.5 KB)

I figured out the solution to this problem.

[LIST=1]
*] Right click on the “Generate Programming File” process
*] navigate to Process Properties ->Configuration Options
*] Find the “-g UnusedPin” setting and change it to “Float”
[/LIST]
I saw this message in the readme.txt file, but as the “first.v” project worked fine without this option, I didn’t try this on the pipetest project.

It would be nice to put this in the FrontPanel-UM.PDF manual, with a warning in large letters that [COLOR=“DarkRed”][SIZE=“6”]THIS WILL BLUESCREEN YOUR PC[/SIZE][/COLOR] if you don’t.

An even better way of fixing this is to modify the core using UCF&HDL to specifically assign high Z to all the unused pins. See http://projects.varxec.net/fpgaunusedpins