I am not a strong FPGA programmer (I’m actually on the software side of things, but I’m trying to set up a demo), so I have some questions that might seem silly.
I want to setup a demo that writes a sine wave over the USB port. I wrote the VHDL component that will generate the sine wave data.
However, I do not understand how to pass the data from the output of my VHDL component to the USB interface. Do I need all of these endpoint types? Do I just need okHostInterfaceCore? I suppose I am just confused about how to use these libraries…any help is greatly appreciated.
As with software, there are several ways of accomplishing what you want, depending on the speed and efficiency you want to accomplish.
As a simple example, you could:
Write the sine wave to a BRAM (block RAM) internal to the FPGA.
Perform a TriggerOut (to activate your software to download the memory)
On the software side, ReadFromPipeOut to transfer the memory contents
On the hardware side, attach the BRAM to the PipeOut
This requires that the full sine wave be written before being tranferred. You could also generate it “on the fly” as long as your generator can work as fast as the PipeOut requires the data (up to 48 MHz).
Finally, you could use the BufferedPipeOut (which provides an asynchronous FIFO between the host and your design). You could then write the sine wave to the BufferedPipeOut as the samples become available. Then have the PC transfer data when the buffer starts to fill up. This will also require the PC to occasionally poll the buffer status to determine how much data is available. The buffer status could be sent to the PC using WireOuts.
Does this help?
I think I see what you are saying. I read the documentation and have come up with the following.
In my design I will need the following:
– okHostInterface
– okTriggerOut
– okBufferedPipeOut
– Custom Sine Wave Generator
The custom sine wave generator creates the data for a sine wave, and writes it to the okBufferedPipeOut component using EP_ADDR, EP_WRITE, and EP_DATAIN for the writing.
When okBufferedPipeOut is full, it will set the EP_FULL output pin high, which will act as the EP_CLK for the okTriggerOut. This trigger is used to tell the software running on the host to read the data.
Does this sound correct?
All except that last bit. The TriggerOut is designed to signal the host when a single-cycle event occurs. That is, a clock is running continuously and at some point, another input signal (EP_TRIGGER) is asserted for a cycle. It’s designed to “catch” the assertion of a DONE signal or some other short-term signal.
You could, however, use a WireOut for the EP_FULL signal – since EP_FULL is asserted when the buffer is full and stays asserted until the buffer isn’t full. You could also use the EP_STATUS signals.