Hi Everyone,
I’m using XEM3010-1500 and there are some weird problem associated digital output pins. So I have 16 pins (xbus) configured as digital output pin, signal frequency is around 10MHz. And I have four modules “Ch1.v, Ch2.v, Ch3.v, and Ch4.v” to specify the output pattern. Each module controls 4 pins. Currently all four modules are exactly the same behavior. But when I download the bit file onto the board, sometimes 4 pins from one module will fail to output the specified waveform. And the failure pins will change if I change the module code a little bit. Basically the failed output pins stops to output data, or miss some transitions.
Does anyone experience similar problems? I want to know what’s wrong with the board. It looks to me like the FPGA chip output driver is not strong enough, or the board wiring is seeing some ringing.
Thanks.
Behavior changes with minor code changes are often indicative of an unreliable HDL design or one that does not meet timing. State machines may get “stuck” in such situations. One of the best ways to debug live designs is with Chipscope.
The FPGA output drivers are programmable and, I think, default to 8mA or so. The outputs and their capabilities are documented in the Xilinx Users Guides.
[QUOTE=Opal Kelly Support;3727]Behavior changes with minor code changes are often indicative of an unreliable HDL design or one that does not meet timing. State machines may get “stuck” in such situations. One of the best ways to debug live designs is with Chipscope.
The FPGA output drivers are programmable and, I think, default to 8mA or so. The outputs and their capabilities are documented in the Xilinx Users Guides.[/QUOTE]
But when it broke, it’s usually one module that is having problem. All four modules (Ch1.v ~ Ch4.v) are the exact same code. Is this also because of the unreliable design? Could it be the problem of the board? Thanks.
Anything is possible at this point – we don’t have much information to go by. We don’t know what your design looks like.
Why not try something really simple? Just put a counter in the design and string the counter bits out to the I/O and see what they look like on a scope.
What are the I/Os hooked up to? It’s possible that the other side has somehow damaged the FPGA, but again – without more information we have not much to go on.