I have a problem with the build .bit file. I started to synthesis. but I can not solve the problem “TTRIG_DELAY” in “okWireIn.vhd”
ERROR:HDLParsers:1015 - “C:/Users/TEST_2/frontpanel_lib/Simulation/okTriggerIn.vhd” Line 47. Wait for statement unsupported.
I know that we should be putting them in two different files, one for synthesis and the other for simulation. However, I have this error.
Could you help me?
The source file you mention is a simulation file. It is not intended to be synthesized.
Yes, I know, the Xilinx employee recommend saving in two different files, How can I synthesis my files, without these files?
because ISE sends a message the okWireIn.vhd could not find and stop the synthesized.
In the end, I want to make a bit file for load in an FPGA, which connect to MATLAB, and FPGA Read/Set the data.
Steps of Process:
Load default parameter to FPGA ==> Set data ==> send signal to MATLAB for analysis ==> Read data from MATLAB
Please start with our FrontPanel documentation here:
https://docs.opalkelly.com/display/FPSDK/FrontPanel+SDK
Notably, you’ll want to review and understand the FrontPanel HDL section.
Several samples have been included with the FrontPanel SDK to give you some working references.