I’ve tried the SDRAM controller sample, for the XEM3010 demo board.
It works fine, but I’ve noticed the following issue :
it seems that the SDRAM memory controller is OK with the Verilog version, but causes some write/read errors with the Vhdl version.
I’ve tried the 2 versions with the same original PC sample soft (“RAMTester.exe”). It generates no error with the bit file “ramtest-1000.bit” (renamed “ramtest.bit”).
But it gives some erros (about 10 with 90 trials of full SDRAM write/read) with the Vhdl bit file, compiled from the files “VHDL Memory controller”.
Have someone noticed this problem ?
Can you please help me in solving it ?