VHDL ramtest example

Is there an example of ramtest in Vhdl for the XEM3005 ?
Thank you


No, the SDRAM controller is only written in VHDL.

Note that XST is perfectly capable of synthesizing mixed-language projects. In other words, the rest of your project can be VHDL even though the SDRAM controller is Verilog.

Line-by-line translation of the Verilog to VHDL would be relatively straightforward.