VHDL Example for Tutorial Part IV

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1

Hi,

Is there an example using VHDL instead of Verilog?

It’s great that there are examples using VHDL.
Then, when I try to simulate, It’s in Verilog, which I don’t quite understand .
It would be nice if there was a VHDL example.

Thanks,

2

No, the simulation files have only been written in Verilog. If you end up writing the same in VHDL, I’m sure other would appreciate it if you posted it to the “Contributions” forum.

3

Hi,

I found a file called dut_tf.vhd, which seems to be the VHDL equivalent of the Verilog test.

I am trying to get that to work with the PipeTest.vhd example.

I am able to load the libraries fine, but when I compile the okLibrary.vhd file,
it creates 2 directories.

  1. okHostInterface
  2. okHostInterfacecore

The library for okHostInterface is included, but there is no library for okHostInterfacecore. So when I try run the macro: “do vhdl_do.do”, it
complains that their is no architecture for okHostInterfacecore.

\okHostInterface

  • _primary.dat
  • _primary.dbs
  • arch.dat
  • arch.dbs

\okHostInterfacecore

  • _primary.dat
  • _primary.dbs

Thanks,