Verilog for okLibrary modules


Is the verilog code for the modules defined in okLibrary available?
I’m thinking that you may have closed the source. Is this is why the
ngc files are provided? What do we do when using ISE8.1i and
ncverilog? Is there documentation on what each module is supposed to
do so that we can write and/or modify our own if needed? I recently
bought a board, but I don’t think I can use it if I don’t have access
to the verilog code.


You are correct that source is not provided for our host interface.

The NGC files work just fine with ISE 8.1i.

As far as I know, no other tool vendor provides map/place/route capability for Xilinx device targets. Therefore, no matter what, you will need to go through the Xilinx back-end tools which will “link” properly with the NGC files we provide.

NC-Verilog requires use of the Xilinx back-end, correct?