In the FrontPanel User’s Manual, I’m looking at the description of how okPipeIn and okPipeOut are used, on pages 37 and 38. The timing diagram on 37, for okPipeIn seems clear enough, and I gather that I can store incoming data to RAM if I do something like this:
always @(negedge ti_clk) begin
if (1 == ep_write) begin
ram[addr] = ep_dataout;
addr = addr + 1;
Now look at the diagram on page 38, for okPipeOut. According to that waveform, ep_data is delayed by a clock tick. Is this correct or is the diagram in error?
I would simply try it and discover for myself, but I’m in the middle of learning HDL based design, and I think posting this will get me an answer sooner than I can get all the hardware and software together for an experiment.