I have a question regarding the use of REAL in VHDL. It’s not an issue with the XEM but I suppose you know the answer and this might help other users facing the same situation as well.
For instance in Counters.vhd, if before the begin in “architecture arch of Counters is”, I add:
signal a : real;
I get the following:
Analyzing Entity (Architecture ).
ERROR:Xst:1547 - “D:/Temp/Xilinx/Samples/Counters/VHDL/Counters.vhd” line 38: Signal of type real is not supported.
and a search in the Xilinx support site returns:
Your search - “Xst:1547” - did not match any documents.
No pages were found containing "“Xst:1547"”.
Please can you help me. Many thanks in advance.