I have a question regarding the use of REAL in VHDL. It’s not an issue with the XEM but I suppose you know the answer and this might help other users facing the same situation as well.
For instance in Counters.vhd, if before the begin in “architecture arch of Counters is”, I add:
signal a : real;
I get the following:
Analyzing Entity (Architecture ).
ERROR:Xst:1547 - “D:/Temp/Xilinx/Samples/Counters/VHDL/Counters.vhd” line 38: Signal of type real is not supported.
and a search in the Xilinx support site returns:
Your search - “Xst:1547” - did not match any documents.
No pages were found containing "“Xst:1547"”.
Unfortunately, I don’t know the true nature of Xilinx’s support for REAL in VHDL. However, I would suspect it to be pretty shallow. What exactly are you trying to do? Since REAL involves potential floating-point representation, it could be difficult to synthsize stuff with it.
Unfortunately, I don’t know the true nature of Xilinx’s support for REAL in VHDL. However, I would suspect it to be pretty shallow. What exactly are you trying to do? Since REAL involves potential floating-point representation, it could be difficult to synthsize stuff with it.
REAL is supported in “functions for constant calculations”[/QUOTE]
Hi Jake,
Thanks so lot for your reply. I was afraid of that.
I’d like to do some floating-point calculations with the FPGA, but may be I’m thinking too much as the software guy I am.
I suppose a possibility could be to install Xilinx MicroBlaze and I suppose their C compiler supports floating-point representation but this is all unchartered territory to me. I have to take a closer look before forking out some $500 for the Xilinx EDK annual license…
Let’s talk about your application (if you don’t mind). In many cases, a floating-point realization is not required. I may be able to suggest some more FPGA-friendly implementations.
If this is sensitive information, you can email me if you like.
Let’s talk about your application (if you don’t mind). In many cases, a floating-point realization is not required. I may be able to suggest some more FPGA-friendly implementations.[/QUOTE]
Hi Jake,
My app transfers audio data from the PC to the FPGA connected to a modulator before driving a digital amp. Next I would like to implement a digital crossover and convolver in the FPGA.
I’ll take a look to implement the crossover (a butterworth filter) with fixed-point.
Thank you again for your help and support, I appreciate it very much.
IIR filters can easily be implemented using fixed-point arithmetic. The 18-bit multipliers on the Spartan-3 will help quite a bit in that respect. The only real concern with fixed-point in IIR filters (aside from precision) is that they can result in “limit cycles” – noise brought on by the feedback and precision limitations. Fortunately, they aren’t much of a concern for most applications.
Here’s a brief article on that. The Rice Connexions database is really useful for DSP/comm topics.
Just a comment on this topic: the type REAL is also used by MATLAB VHDL Filter generator (quite simple to use).I compiled one of those and it makes a huge module with REAL type of input and output. Maybe it can be used with as a coprocessor for main processor (Power PC or MicroBlaze).
I will have to use FIR filter for my project. Jake, do you have any suggestions?
I would recommend using fixed-point for an FIR filter. There is generally little reason to go beyond integer math for an FIR filter in most applications. The Spartan-3 (and others) have built-in 18-bit multipliers which, again, are adequate for many applications.
I have not used the Matlab HDL generator, but am quite surprised it would instantiate that sort of multiplication. It should be aware of the built-in mults on the device. Are you certain it has been setup correctly? Can you better constrain your inputs and outputs so that it will use fixed-point math?
Just a comment on this topic: the type REAL is also used by MATLAB VHDL Filter generator (quite simple to use).I compiled one of those and it makes a huge module with REAL type of input and output.
— End quote
Hi Guru,
Have you been able to check it out and confirm it works (I don’t have Matlab) ? can you do the 4 arithmetic operations with your module ?
[QUOTE=Opal Kelly Support]Patrick-
In many cases, a floating-point realization is not required. I may be able to suggest some more FPGA-friendly implementations.QUOTE]
Hi Jake,
I would like to ask for your advice.
I rewrote the IIR filter code for a fixed-point implementation but now I’m facing an unexpected problem: I need to do a certain number of multiply operations, but I’m exceeding the Spartan multipliers count.
I tried to invoque a multiply operation as a procedure called repeatedly. I also tried with arrays in a loop but everytime, multipliers get allocated instead of being re-used.
I suppose I can use a process with a clock which on each pass does a multiply until completion of the whole calculation but I’m wondering whether there is an easier method with VHDL.
What is the clock rate of your filter? How many biquads are you performing per sample? Your post suggests that you’re trying to time-share the multipliers, right?
You could build an IIR filter biquad block using a pair of small memories (made from distributed memory). The memories would store the states of the biquad. You could then use a relatively simple state machine to set the addresses to the memories appropriately on each successive clock.
You could time-share without the memories by using mux’s. In any case, the timesharing will need to be explicit in the HDL. I just don’t think the synthesis tools are smart enough yet to set this sort of thing up. With some of the higher-level tools like Confluence or System-C, this may be possible, but I don’t know those tools.
What is the clock rate of your filter? How many biquads are you performing per sample? ?
— End quote
Hi Jake,
Thank you for your reply.
Audio output rate is 44100 or 88200. For a 4-way stereo system, there are 4 x 2 IIR filters (crossovers). The number of multiply operation depends on the filter order.
— Begin quote from Opal Kelly Support
Your post suggests that you’re trying to time-share the multipliers, right?
— End quote
Yes, at this point this is the only method that I can think about. Hence my question since I’m a real HDL beginner: is there another way to re-use an already allocated multiplier ?
Not that I’m aware of… The only alternatives I could think of would be to use Confluence or some tool like that. Basically, these sorts of tools allow you to work at a higher level than the HDL provides.
I had a problem that took me quite some time to figure out and describing it here might help users coming across a similar situation.
As per Jake’s advice, I rewrote my IIR filter to use fixed-point arithmetic but I hit the limitation of not having enough 18-bit multipliers on the Spartan-3.
I then modified the HDL code to time-share the multipliers but the results I got back were pretty weird and absolutely not consistent and that was driving me crazy.
I finally figured out that I was doing a multiply operation on every rising edge of ti_clk but that was too fast for the multipliers. My problem was solved after dividing ti_clk by 2.
Interesting… The Spartan-3 multipliers work just fine well above 100 MHz. I admit, though, I don’t quite know what XST does to add resource sharing. Perhaps it just requires -some- 2x clock from somewhere.