I can transfer data using pipes from my PC to the FPGA at around 25MB/s (for short bursts of data). However I am trying to send several bursts of data using seperate calls to WriteToPipe yet its takes 400uS between each burst which is at least 400 times slower than I was hoping for.
What I am trying to do is send some setup information to the FPGA, it will then control my hardware and return a few words of data, and do this repeatably in a cycle time of less than about 4uS for at least 320 cycles.
The only way around this at the moment I can see is to provide all the setup info in advance and then return all the result data at once. This is going to massively increase the amount and complexity of VHDL I am going to have to write as I intended to run most of the control from my PC.
Anyone got any ideas ?