I have just finished implementing functionality that keeps track of the number of events sent. Essentially i have given each timestamp a count which is also transmitted as the upper 8 bits of each 32-bit timestamp so:
|—8 bit event counter—|---24 bit time stamp----------------------|
when using this i have found that i am consistantly dropping 17 time stamps at random intervals. This makes sence in terms of packet loss, as i am requesting 64bytes at a time which corrisponds to 16 time stamps. Though i am not sure where the last one goes either.
Ok, so that kinda makes sence, i just can’t find the cause, but now things get really weird…To explain, i need to first describe a bit about the rest of the FPGA usage.
The FPGA is split into two sections which are independantly controlled through the endpoints. The first is the recording mechanism which time stamps incomming asynchronous pulses and then sends these timestamps to the PC via a FIFO buffer and your endpoint. The second section is a computational model that produces pulses 1ms wide at semi-random intervals of between 0 > 40 Hz.
To test both parts at the same time, i have connected the output from the second section into the input from the first. And it is in this configuration that i miss data. The data is produced from the second part, as is seen by a logic analyser that i am using. Additionally, because of the new code i have implemented, it is possible to see when data is being lost.
However, if i connect up a signal generator to the input instead of shorting the output to the input by a single wirel, no data is lost. Do you have any ideas why this is?