I’m trying to build the frontpanel sample files, eventually wanting to use the frontpanel features with custom code. I started with just the samples as directed in the README.txt for the XEM7001, but I cannot generate bitfiles with any of the samples in verilog or VHDL. The tool I am using is Vivado 2021.1.
The problem appears to be the blackbox FrontpanelHDL modules, it looks as if Vivado is having trouble reading the encrypted files. Despite all verilog and constraint files being added to the project (and copied into the project directory) I either get “missing module” errors or errors from the encrypted envelope:
- [Synth 8-5809] Error generated from encrypted envelope. ["…/Counters.srcs/okCoreHarness.v":14]
I’ve managed to get through synthesis with only one combination of files → the “First” example in VHDL (but not in verilog). But after achieving this the implementation fails because none of the blackbox modules are placed or routed during synthesis. This generates the errors below:
- [Opt 31-31] Blackbox ep01 (okWireIn) is not supported or not found. This blackbox cannot be found in the existing library.
- [Opt 31-30] Blackbox ep00 (okWireIn) is driving pin I0 of primitive cell led_OBUFT_inst_i_1. This blackbox cannot be found in the existing library.
- [Opt 31-236] Found primitives driven by Empty Hierarchy Cells/Black boxes.
These are the warnings generated when the VHDL code synthesizes, with matching ones for each FrontpanelHDL module (okWireIn, etc):
- [Project 1-486] Could not resolve non-primitive black box cell ‘okCoreHarness’ instantiated as ‘okHI/core0’ [C:/…/sources_1/okLibrary.vhd:145]
I feel like I must be missing something about the FrontpanelHDL files. Has anyone experienced problems with the samples in the past? Any help would be greatly appreciated.