UCF constrains for XEM3010

What constrains are required in the UCF file to handle the requirements of the OpalKelly IP and the interface with the XEM3010 hardware (e.g. USB interface). (I have not migrated yet to FP 3).


1.I am using location constrains such as this one (based on FP examples):

NET “hi_addr” LOC = “R8”;

TheXilinx flow considers this pin to be LVCMOS25 by default. Do we need to constrain it to be LVCMOS33?

2.The only timing constrain in my UCF file is:

NET “hi_clk” TNM_NET = “hi_clk”;
TIMESPEC “TS_hi_clk” = PERIOD “hi_clk” 20 ns HIGH 50 %;

Do I need timing constrains for the offset between the hi_clk clock and the data lines of the USB interface (e.g. hi_addr<>)? I assume that the external USB interface expects some timing relation between the hi_clk and the data lines.




The LVCMOS25 constraint is fine. Internally, I believe both LVCMOS33 and LVCMOS25 are identical. The only difference is that the VCCO voltage applied externally will differ.

Regarding timing constraints – you may want to put a 48MHz constraint on the hi_clk (or ti_clk), but we have found that this is generally not necessary unless you are using a lot of endpoints in your design. 48 MHz doesn’t represent much of a challenge for the Spartan-3.

But it certainly doesn’t hurt and would add a little confidence to your timing analysis.