I am trying to reconcile the RAMtester example simulation results with the timing diagrams found in the MIG user guide.
I have the following questions:
*]Are the addresses specified by app_af_addr [30:0] word vs byte addresses? The simulation increments the address by 4, which if byte address is on longword, if word address is 2 longwords.
*]In figure 9-12 (Page 390), the timing diagram shows app_af_wren asserted along with app_af_addr and ap_wdf_wren. In the RAMtester simulation, both ap_af_wren and ap_af_addr are offset by one clock cycle. (I’ve attached a snapshot).
*]The 9-12 timing diagram latches in 4 distinct address. The RAMtester only latches 2. Both examples are supposedly for Writes with a burst length of 4.
RAMTester_MIG_WRITE_BURST.jpg (48.9 KB)