Trouble integrating FrontPanel in LabVIEW

Opal Kelly does not officially support LabVIEW for FrontPanel, but I hope someone cam offer some suggestions.

Running under Windows XP, I have an XEM3010-1500P attached via USB, and can successfully configure and control it from the FrontPanel GUI.

From LabVIEW (2010), I started with Counter.vi from the LABVIEW samples.
That failed, without much in the way of information.
Since it was written for an older API revision, I decided to import the libraries and incrementally build a simple VI, paralleling its calls.

I followed the import steps in the 12-28-2010 Forum postings, LabView FrontPanel DLL Import and all the okFrontPanel User Library Vis imported, apparently with no problems, but I have not gotten even a very simple initialization VI working.

Construct.vi returns a handle, apparently time based, differing with each call
Open By Serial.vi returns a decimal string, equal to FFFF FFFF (-1, Int32), and the same handle out as was passed in, regardless of the device number string passed to it (0, 1, 2, 1IW [sticker on the module], etc.).
Get Device Major Version.vi returns -1, as does Get Device Minor Version.vi

It appears that Open By Serial is failing, but I don?t have a clue as to why!

I would be very grateful for any help!

Dave

Hi

If you stop VI’s in Labview, it will keep open the line to the DLL and to the FPGA.
Starting the VI again it will fail on the okFrontPanel_Construct because the old connection still exists in memory.
Do not use the stop button of Labview but make your own stop button and let the VI call the function okFrontPanel_Destruct before returning to the edit mode.
Else you have to disconnect and reconnect the USB-device again and again many times…

— Begin quote from dutchcompo;3297

If you stop VI’s in Labview, it will keep open the line to the DLL and to the FPGA.

— End quote

Thanks for the reply, Dutch!

I finally figured that out, but was really getting frustrated until then.
A couple of things led to not catching it sooner:
The description of okOpenBySerial() (I believe it was) included the comment that no Close call was required. I conflated this with Construct not needing an equivalent.
When I opened the block diagram of an example VI, the Destruct sub-VI was just off screen, outside the main loop, and I plain didn’t see it!

Dave

Hi

I saw also this function: okUsbFrontPanel_IsOpen(okUSBFRONTPANEL_HANDLE hnd);
A construction to find out if the VI was already started with “First Call?” is possible and then decide to “construct and open” or not.
I found a solution my way. This because I use mostly CVI to communicate with the FPGA. And I want to be sure I can use the FPGA inside my CVI environment.

dear Dave
i am using Xem 3010 with labview 8.6
i am trying to read from ram, but it does not work
but Construct.vi, and Open By Seria… work very well
please try my lib. i think i could useful for you
if you have any problem, contact to me, we will work together
after every load .bit file into fpga , you need unplug fpga’s power supply.

my email: ndhoang@iop.vast.ac.vn


okFrontPanel-run.zip (636.8 KB)

okFrontPanel-test.zip (16.8 KB)

[QUOTE=ndhoang1985;3326]please try my lib. i think i could useful for you

after every load .bit file into fpga , you need unplug fpga’s power supply.
[/QUOTE]

Thank you very much for the reply and the library uploads.
We will give these vi’s a try.

I am curious about the last comment, though.
Why does the FPGA need to be power cycled on .bit load?
And I hope you meant “before” loading the .bit file?

Dave

dear Dave,
i meant after you finished your measurement, you should unplug power supply to reset fpga.
it mean “before” loading the .bit file.
:slight_smile:
sorry about the incorrect information.

[QUOTE=dbell;3327]Thank you very much for the reply and the library uploads.
We will give these vi’s a try.

I am curious about the last comment, though.
Why does the FPGA need to be power cycled on .bit load?
And I hope you meant “before” loading the .bit file?

Dave[/QUOTE]

[QUOTE=ndhoang1985;3332]dear Dave,
i meant after you finished your measurement, you should unplug power supply to reset fpga.
it mean “before” loading the .bit file.
:slight_smile:
sorry about the incorrect information.[/QUOTE]

I’ve not had to unplug the power supply to load/reload the bit file, as long as the destruct (and construct) gets called every time you close the program, or need to load a bitfile.