I have been using the Opal Kelly board and its various functionalities such as WireIn and WireOuts for my project. However, one thing I was wondering is if timing constraints should be defined (or is already defined somewhere?) for all the I/O pins. I am worried that if they are left undefined then the I/O latency may be more or less arbitary. If they are not already defined and they should be, I was wondering if there are any suggestions since the timing constraint statements require explicit delay (ie. 25ns delay).