Trying to do something similar to Transfer data example. The other end-points seem to work but the read and write to pipe are both timing out.
Using Python (3.8) API, and Frontpanel 5.2.2
Where should I start looking to find the problem? I’ve simulated it and that worked perfectly fine.
I’ve added a fifo:
-- Fifo signals
signal epPipeIn_fifo : std_logic_vector(31 downto 0);
signal epPipeWrite_fifo : std_logic;
signal epPipeOut_fifo : std_logic_vector(31 downto 0);
signal epPipeRead_fifo : std_logic;
signal full_fifo : std_logic;
signal empty_fifo : std_logic;
signal reset : std_logic;
component pipe_fifo_32_1024
port (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
With the following end-points:
okWO : okWireOR generic map (N=>2) port map (okEH=>okEH, okEHx=>okEHx);
ep00 : okWireIn
port map (
okHE=>okHE,
ep_addr=>x"00",
ep_dataout=>ep00wire);
ep10 : okWireIn
port map (
okHE=>okHE,
ep_addr=>x"10",
ep_dataout=>ep10wire);
-- from SW input
epPipe_into_fifo : okPipeIn
port map (
okHE => okHE,
okEH => okEHx( 1*65-1 downto 0*65 ),
ep_addr => x"81",
ep_dataout => epPipeIn_fifo,
ep_write => epPipeWrite_fifo);
-- fifo
pipe_fifo_inst1 : pipe_fifo_32_1024
port map (
clk => okClk,
rst => reset,
din => epPipeIn_fifo,
wr_en => epPipeWrite_fifo,
rd_en => epPipeRead_fifo,
dout => epPipeOut_fifo,
full => full_fifo,
empty => empty_fifo);
-- to Sw output
epPipe_out_of_fifo : okPipeOut
port map (
okHE => okHE,
okEH => okEHx( 2*65-1 downto 1*65 ),
ep_addr => x"a1",
ep_datain => epPipeOut_fifo,
ep_read => epPipeRead_fifo);