Synthesizing the DES code

I’m trying to get the Verilog code that came with the DES example to synthesize. I copied all 13 files from XEM8350-Verilog to a new project folder in my home directory. I created a new project in Vivado, added the folder, selected my board and hit “Run Synthesis” right out the door I get an error [Synth 8-439] module ‘okHost’ not found

That’s not totally surprising. I think the writers of the example are probably expecting the user to figure out that they need to drop in the FrontPanel IP core. I believe there are two common options for doing this—the IPI designer or the FrontPanel Subsystem IP Core wizard

I go to Window>IP Catalog and start configuring a IP Core.
I see 5 wireIns in DESTop.v so I select that I want 5 WireIns in the IP Core Wizard.
I use the endpoint addresses in the DESTop.v module names(eg 0x08)
I do the same for the 2 trigger ins, the trigger out, the pipe in, and the pipe out.

I try to synthesize and I hit the error okHost not found again. Which is weird because I see that module in okLibrary.v

I’m using Vivado 2022.1.2

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You are very close, except the intention is to simply add the FrontPanel HDL from the FrontPanelHDL\XEM8350-KU060\Vivado-2021 folder, and then build. More details are in the README.txt in the Samples directory. All of our official samples in the Samples folder operate this way.

The reason you see this error is because instantiating the okHost is different between the two flows, either using the Vivado IP core or the FrontPanel HDL. Vivado IP core flow would instantiate, well, the IP you created. Non-Vivado IP core flow essentially instantiates the okHost directly and manually.

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